This disclosure relates generally to integrated circuits, and more particularly to a bond pad structure.
Integrated circuits are typically formed on a substrate such as a semiconductor wafer. Bond pads (or bonding pads) are included on the substrate. A bond pad provides an interface to an integrated circuit device through which an electrical connection to the device may be made. Conventional techniques may be used to provide a connection from a package terminal to an integrated circuit using the bond pad such as, thermocompression or thermosonic wire bonding, flip chip techniques, and other techniques known in the art.
Interconnection techniques can cause mechanical stress to the bond pad structure and surrounding areas, for example, from the placement of a ball or wedge in wire bonding or a bump in flip chip techniques onto the bond pad. Additionally, in an electrical test procedure, a bond pad may be used to provide connection to an underlying integrated circuit device in order to analyze the device. The contact of a test probe during the test procedure can also cause mechanical stress to the bond pad structure. The stress from bonding, electrical test, as well as from other possible stress sources, may cause damage to the bond pad structure as well as the underlying layers. Examples of types of damage that may occur include cracking and delayering. The stress is particularly critical as semiconductor technology progresses because layers underlying the bond pad area, for example, interlayer dielectrics having a low dielectric constant, are becoming more and more fragile.
As such, an improved bond pad structure is desired.